搜索资源列表
altpcie_64b_x8_pipen1b
- PCIE的软核程序，基于Verilog HDL语言，应用于FPGA的高级编程应用中。-PCIE soft nuclear program, based on Verilog HDL language, used in high-level FPGA programming applications.
code
- 一个基于fpga的简单的实时心电检测系统，包括与pc通讯和qrs检测两部分-A simple fpga-based real-time ECG detection system, including communication with the pc and qrs detection of two parts
Asynchronous_slavefifo.v
- data trasfer from fpga to usb device developed in vhdl format
V35interface-communicate
- V.35接口与E1接口之间转换的基本原理,介绍了E1信道分时隙通信的基本过程，叙述了基于FPGA用VHDL和QuartusII来仿真本系统设计与实现的过程。-V.35 interface and E1 interface to convert between the basic principles of E1 channel introduces the basic process of communication sub-time slot, described by VHDL and FP
DE2_LCM_CCD_detect_b
- 本程序基于Altera公司的DE2平台完成仓库的实时监控并对移动的目标进行自动识别和报警的FPGA设计，研究重点就是图像采集和移动目标识别的FPGA实现。采用Altera公司的DC2模版对视频进行采集并将采集到的图像信息进行缓存，通过监视器实时显示，采用帧间差分法对采集到的帧图像进行运动检测，当仓库中有运动情况的时候，两个图像间灰度会出现异常，通过对灰度异常的侦测完成仓库移动目标的识别并蜂鸣器报警。-Complete real-time monitoring of the warehouse a
v-watch
- 基于fpga的数字电压表的设计，包括ad转换，bcd码转换，分频，3选1模块，小数点生成模块，显示模块组成。-Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module.
crc16_8bit.v
- FPGA用于实现crc16编码的verlog源程序，用到的请下载。-FPGA is used to achieve the the crc16 the encoding of verlog source code used to download.
V
- 利用FPGA实现一个乒乓球的小游戏，测试可用-FPGA implementation of a table tennis game
Alrera-FPGA-SOC-Cyclone-V
- Alrera FPGA SOC Cyclone V 官网开发板调试记录-Alrera FPGA SOC Cyclone V official website development board debug log
bin2bcd.v
- FPGA Verilog BIN 2 BCD Conversion code.
aib-01017-soc-fpga-overview
- Altera SOC platform overview for Stratix-V, ArriaV FPGA families, with ARM Cortex A9 Dual COre Hard Macro embedded. This is a seminar document, attended in May 2013
FPGA-KeyboardControl
- 可以y9ng捱三顶四都v大少吃点 阿少吃点奥迪车爱迪生v大dsca点撒-You can y9ng endure three four are v A large eat less eat less Audi Edison v big dsca point spread
uCOS-II-Cyclone-V-SoC
- 应用在ALTERA FPGA芯片的UCOS开发板实现代码,从micrium官网下载-μC/OS-II Example for the Cyclone V SoC Development Kit
br-soc-fpga
- cyclone v的altera公司的带arm硬核的soc设计指南-cyclone v the product of altera with the arm hard process cores introductiong
internal_reset.v
- code for internal reset in fpga
wcdma.v
- 无线通信FPGA设计例13-6源代码，WCDMA系统小区搜索的FPGA实现 -Example 13-6 FPGA design of wireless communication source code, FPGA implementation of WCDMA system cell search
fpga_uart2
- 基于FPGA的.v文件，用于RS232串口通讯，实现简单的自发自收-rs232 data sent and recive for fpga .v
fpga
- internal_types.h,v 1.2 2004 05 06 15:53:39 drahn Exp $.
Altera-Cyclone-V-Memory
- Altera Cyclone V FPGA中的高效能硬核Memory控制器-Altera Cyclone V FPGA ddr3 Memory control
21ic_VIVADO-verilog
- vivado 下的可逆计数器项目，使用VERILOG语言编写，基于FPGA -vivado 下的可逆计数器项目，使用VERILOG语言编写，基于FPGA v